1. Field of the Invention
This invention relates to an imaging apparatus.
Priority is claimed on Japanese Patent Application No. 2012-174035, filed Aug. 6, 2012, the content of which is incorporated herein by reference.
2. Description of Related Art
As one example of an imaging apparatus using a time to digital converter (TDC) type of Analog to Digital (AD) conversion circuit, a configuration described in Japanese Unexamined Patent Application, First Publication No. 2008-92091 and Japanese Unexamined Patent Application, First Publication No. 2009-38726 have been known.
FIG. 5 shows a part excerpted from the configuration of the TDC type of AD conversion circuit according to a conventional example. First, the configuration and operation of a circuit of FIG. 5 will be described.
The circuit illustrated in FIG. 5 includes a clock generation unit 1018, a comparing unit 1109, a latch unit 1108, a counter 1105 and a buffer circuit BUF. The clock generation unit 1018 has a plurality of delay units DU[0] to DU[7] which delay and output an input signal. A start pulse (=StartP) is input to the leading delay unit DU[0]. The comparing unit 1109 has a voltage comparator COMP which receives an analog signal SIG which is a target of AD conversion and a ramp wave Ramp which decreases with lapse of time, and outputs a comparison output CO based on the result of comparison of the analog signal SIG with the ramp wave Ramp. The latch unit 1108 has latch circuits L—0 to L—7 which latch logic states of output clocks CK[0] to CK[7] from the clock generation unit 1018. The counter 1105 has a counter circuit CNT which performs counting based on the output clock CK[7] from the clock generation unit 1018. A control signal RST is a signal for performing a reset operation of the counter circuit CNT.
In the comparing unit 1109, a time interval (a magnitude of the time axis direction) corresponding to the amplitude of the analog signal SIG is generated. The buffer circuit BUF is an inversion buffer circuit which inverts and outputs the input signal. Here, in order for the description to be readily understood the specification, the buffer circuit BUF is configured of an inversion buffer circuit.
The latch circuits L—0 to L—7 constituting the latch unit 1108 are in an enable (valid, active) state when an output signal Hold of the buffer circuit BUF is in a high state (H state), and the output clocks CK[0] to CK[7] from the delay units DU[0] to DU[7] are output as is. Further, the latch circuits L—0 to L—7 are in a disabled (invalid, hold) state when the output signal Hold of the buffer circuit BUF transitions from a high state (H state) to a low state (L state), and at this time, latch the logic states corresponding to the output clocks CK[0] to CK[7] from the delay units DU[0] to DU[7].
Next, the operation of the conventional example will be described. FIG. 6 illustrates the operation of a conventional example. In FIG. 6, Q0 to Q7 indicate signals output from the latch circuits L—0 to L—7 of the latch unit 1108.
First, at a timing according to the comparison start of the comparing unit 1109, as a start pulse (=StartP), a clock having a period approximately equal to a delay time of the clock generation unit 1018 is input to the clock generation unit 1018. Thereby, the delay units DU[0] to DU[7] of the clock generation unit 1018 start operations. The delay unit DU[0] inverts and delays the start pulse (=Startp) and output the inverted and delayed start pulse as the output clock CK[0], and the delay units DU[1] to DU[7] respectively invert and delay the output clocks from the delay units in the previous stages to output the inverted and delayed output clocks as the output clocks CK[1] to CK[7]. The output clocks CK[0] to CK[7] from the delay units DU[0] to DU[7] are input to the latch circuits L—0 to L—7 of the latch unit 1108. Since the output signal Hold of the buffer circuit BUF is in an H state, the latch circuits L—0 to L—7 are in an enabled state and output the output clocks CK[0] to CK[7] from the delay units DU[0] to DU[7], respectively.
The counter 1105 performs a counting operation based on the output clock CK[7] output from the latch circuit L—7 of the latch unit 1108. In this counting operation, a count value increases or decreases along with rising or falling of the output clock CK[7]. At a timing at which the analog signal SIG and the ramp wave Ramp are approximately equal, the comparison output CO is inverted. After the comparison output CO is buffered in the buffer circuit BUF, the output signal Hold of the buffer circuit BUF is in an L state.
Thereby, the latch circuits L—0 to L—7 enter a disabled state. At this time, the logic states corresponding to the output clocks CK[0] to CK[7] from the delay units DU[0] to DU[7] are latched in the latch circuits L—0 to L—7. The counter 1105 latches a count value when the latch circuit L—7 stops its operation. The data corresponding to the analog signal SIG can be obtained by the logic state latched by the latch unit 1108 and the count value latched by the counter 1105.
In Japanese Unexamined Patent Application, First Publication No. 2012-39386, realization of low current consumption of the TDC type of AD conversion circuit has been proposed in which a latch control unit which controls the operation of the latch unit 1108 is installed, the analog signal SIG and the ramp wave Ramp approximately coincide, the latch unit 1108 is in an enabled state at a timing (comparison end timing) at which the comparison output CO is inverted, and the latch unit 1108 is in the disabled state at a timing at which a predetermined time has lapsed from the comparison end timing.
FIG. 7 illustrates an operation described in Japanese Patent Application, First Publication No. 2012-39386. In FIG. 7, the latch circuits L—0 to L—6 stop operations until the comparison end timing at which the comparison output CO is inverted. The latch circuits L—0 to L—6 enter an enabled state at the comparison end timing. Subsequently, the latch circuits L—0 to L—7 enter a disabled state at a timing at which a predetermined time has lapsed from the comparison end timing. In the above operation, since the latch circuits L—0 to L—6 operate during only the time period until a predetermined time has lapsed from the comparison end timing, it is possible to reduce the consumption current.